mitll_DFF_ws workspace

Family: DFF Reference: mitll_DFF Backend: josim Cached
View reference

Parameters

Physical: Dimensions: 30.1 × 70.05 µm  |  JJs: 7  |  Delay: 1.0–3.0 ps
NameExpressionPhysicalUnitSourceNotes
BiasCoef axis manifest-axis sweep axis: bias_coef
IC axis manifest-axis sweep axis: jj_ic
data_input_activity_present.min_count 6 manifest-expectation expectation threshold
clock_activity_present.min_count 8 manifest-expectation expectation threshold
latched_output_activity_present.min_count 4 manifest-expectation expectation threshold
output_follows_latched_state_with_delay.min_delay_ps 1.0 ps manifest-expectation expectation threshold
output_follows_latched_state_with_delay.max_delay_ps 3.0 ps manifest-expectation expectation threshold
▶ Cell Internals — JJ Inductor Resistor
G PORT_A a PORT_CLK clk PORT_Q q E_B1 B1 E_LB1 LB1 E_B1--E_LB1 E_L1 L1 E_B1--E_L1 E_L2 L2 E_B1--E_L2 E_LP1 LP1 E_B1--E_LP1 E_RB1 RB1 E_B1--E_RB1 E_B2 B2 E_B3 B3 E_B2--E_B3 E_LB2 LB2 E_B2--E_LB2 E_B2--E_L2 E_L3 L3 E_B2--E_L3 E_RB2 RB2 E_B2--E_RB2 E_LRB2 LRB2 E_B2--E_LRB2 E_RB3 RB3 E_B2--E_RB3 E_B3--E_LB2 E_B3--E_L3 E_LP3 LP3 E_B3--E_LP3 E_B3--E_LRB2 E_B3--E_RB3 E_B4 B4 E_B6 B6 E_B4--E_B6 E_B4--E_L3 E_L6 L6 E_B4--E_L6 E_LP4 LP4 E_B4--E_LP4 E_RB4 RB4 E_B4--E_RB4 E_LRB6 LRB6 E_B4--E_LRB6 E_B5 B5 E_LB3 LB3 E_B5--E_LB3 E_L4 L4 E_B5--E_L4 E_L5 L5 E_B5--E_L5 E_LP5 LP5 E_B5--E_LP5 E_RB5 RB5 E_B5--E_RB5 E_B6--E_L3 E_B6--E_L5 E_B6--E_L6 E_B6--E_RB4 E_RB6 RB6 E_B6--E_RB6 E_B6--E_LRB6 E_B7 B7 E_LB4 LB4 E_B7--E_LB4 E_B7--E_L6 E_L7 L7 E_B7--E_L7 E_LP7 LP7 E_B7--E_LP7 E_RB7 RB7 E_B7--E_RB7 E_IB1 IB1 E_IB2 IB2 E_IB1--E_IB2 E_IB3 IB3 E_IB1--E_IB3 E_IB4 IB4 E_IB1--E_IB4 E_IB1--E_LB1 E_IB1--E_LP1 E_IB1--E_LP3 E_IB1--E_LP4 E_IB1--E_LP5 E_IB1--E_LP7 E_LRB1 LRB1 E_IB1--E_LRB1 E_LRB3 LRB3 E_IB1--E_LRB3 E_LRB4 LRB4 E_IB1--E_LRB4 E_LRB5 LRB5 E_IB1--E_LRB5 E_LRB7 LRB7 E_IB1--E_LRB7 E_IB2--E_IB3 E_IB2--E_IB4 E_IB2--E_LB2 E_IB2--E_LP1 E_IB2--E_LP3 E_IB2--E_LP4 E_IB2--E_LP5 E_IB2--E_LP7 E_IB2--E_LRB1 E_IB2--E_LRB3 E_IB2--E_LRB4 E_IB2--E_LRB5 E_IB2--E_LRB7 E_IB3--E_IB4 E_IB3--E_LB3 E_IB3--E_LP1 E_IB3--E_LP3 E_IB3--E_LP4 E_IB3--E_LP5 E_IB3--E_LP7 E_IB3--E_LRB1 E_IB3--E_LRB3 E_IB3--E_LRB4 E_IB3--E_LRB5 E_IB3--E_LRB7 E_IB4--E_LB4 E_IB4--E_LP1 E_IB4--E_LP3 E_IB4--E_LP4 E_IB4--E_LP5 E_IB4--E_LP7 E_IB4--E_LRB1 E_IB4--E_LRB3 E_IB4--E_LRB4 E_IB4--E_LRB5 E_IB4--E_LRB7 E_LB1--E_RB1 E_LB2--E_LRB2 E_LB2--E_RB3 E_LB3--E_RB5 E_LB4--E_RB7 E_L1--PORT_A E_L1--E_LB1 E_L1--E_L2 E_L1--E_RB1 E_L2--E_LB1 E_L2--E_RB1 E_L2--E_RB2 E_L3--E_LB2 E_L3--E_L6 E_L3--E_LRB2 E_L3--E_RB3 E_L3--E_RB4 E_L3--E_LRB6 E_L4--PORT_CLK E_L4--E_LB3 E_L4--E_L5 E_L4--E_RB5 E_L5--E_LB3 E_L5--E_RB5 E_L5--E_RB6 E_L6--E_LB4 E_L6--E_L7 E_L6--E_RB4 E_L6--E_LRB6 E_L6--E_RB7 E_L7--PORT_Q E_L7--E_LB4 E_L7--E_RB7 E_LP1--E_LP3 E_LP1--E_LP4 E_LP1--E_LP5 E_LP1--E_LP7 E_LP1--E_LRB1 E_LP1--E_LRB3 E_LP1--E_LRB4 E_LP1--E_LRB5 E_LP1--E_LRB7 E_LP3--E_LP4 E_LP3--E_LP5 E_LP3--E_LP7 E_LP3--E_LRB1 E_LP3--E_LRB3 E_LP3--E_LRB4 E_LP3--E_LRB5 E_LP3--E_LRB7 E_LP4--E_LP5 E_LP4--E_LP7 E_LP4--E_LRB1 E_LP4--E_LRB3 E_LP4--E_LRB4 E_LP4--E_LRB5 E_LP4--E_LRB7 E_LP5--E_LP7 E_LP5--E_LRB1 E_LP5--E_LRB3 E_LP5--E_LRB4 E_LP5--E_LRB5 E_LP5--E_LRB7 E_LP7--E_LRB1 E_LP7--E_LRB3 E_LP7--E_LRB4 E_LP7--E_LRB5 E_LP7--E_LRB7 E_LRB1--E_RB1 E_LRB1--E_LRB3 E_LRB1--E_LRB4 E_LRB1--E_LRB5 E_LRB1--E_LRB7 E_LRB2--E_RB2 E_LRB2--E_RB3 E_LRB3--E_RB3 E_LRB3--E_LRB4 E_LRB3--E_LRB5 E_LRB3--E_LRB7 E_LRB4--E_RB4 E_LRB4--E_LRB5 E_LRB4--E_LRB7 E_LRB5--E_RB5 E_LRB5--E_LRB7 E_LRB6--E_RB4 E_LRB6--E_RB6 E_LRB7--E_RB7

Schematic Open full view ↗

★ curated curated deps/upstream/RSFQlib/RSFQlib/mitll_DFF/THmitll_DFF_v3p0_schematic.sch
1 2 101 3 4 5 104 6 105 7 9 108 8 14 15 114 16 113 13 10 11 110 12 B1 LP1 LRB1 L2 L1 LB1 RB1 IB1 comp_8 comp_9 comp_10 RB2 LRB2 B2 B3 LP3 LRB3 L3 LB2 RB3 IB2 comp_21 comp_22 comp_23 B4 LP4 LRB4 L6 RB4 comp_29 comp_30 B7 LP7 LRB7 L7 LB4 RB7 IB4 comp_38 comp_39 comp_40 LRB6 RB6 B6 B5 LP5 LRB5 LB3 RB5 IB3 comp_50 comp_51 comp_52 L5 L4 ★ curated mitll_DFF

Truth Table

D flip-flop: data pulse is latched on clock rising edge

DClk ↑Q
0pulse0 (unchanged)
pulsepulsepulse (latched)
▶ Testbench connectivity & netlist
Full testbench connectivity view — not a true schematic.
G cluster_dut DUT cluster_tb Testbench N_GND GND E_I_A I_A E_I_A->N_GND N_1 1 E_I_A->N_1 E_XSOURCEINA XSOURCEINA E_XSOURCEINA->N_1 N_2 2 E_XSOURCEINA->N_2 E_XLOADINA XLOADINA E_XLOADINA->N_2 N_3 3 E_XLOADINA->N_3 E_I_CLK I_CLK E_I_CLK->N_GND N_4 4 E_I_CLK->N_4 E_XSOURCEINCLK XSOURCEINCLK E_XSOURCEINCLK->N_4 N_5 5 E_XSOURCEINCLK->N_5 E_XLOADINCLK XLOADINCLK E_XLOADINCLK->N_5 N_6 6 E_XLOADINCLK->N_6 E_XLOADOUTQ XLOADOUTQ N_7 7 E_XLOADOUTQ->N_7 N_8 8 E_XLOADOUTQ->N_8 E_XSINKOUTQ XSINKOUTQ E_XSINKOUTQ->N_8 E_XDUT XDUT E_XDUT->N_3 E_XDUT->N_6 E_XDUT->N_7
Raw netlist
* JSIM deck file generated with TimEx
* === DEVICE-UNDER-TEST ===
* Back-annotated simulation file written by InductEx v.6.1.52 on 2022/08/02.
* Author: L. Schindler
* Version: 3.0
* Last modification date: 1 August 2022
* Last modification by: T. Hall
* Copyright (c) 2018-2022 Lieze Schindler, Tessa Hall, Stellenbosch University
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this cell library and associated documentation files (the "Library"), to deal
* in the Library without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Library, and to permit persons to whom the Library is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Library.
* THE LIBRARY IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE LIBRARY OR THE USE OR OTHER DEALINGS IN THE
* LIBRARY.
* For questions about the library, contact Tessa Hall, 19775539@sun.ac.za.
* The cell is not designed to be connected directly to passive transmission lines.
*$Ports  a clk q
.subckt THmitll_DFF a clk q
.model jjmit jj(rtype=1, vg=2.8mV, cap=0.07pF, r0=160, rn=16, icrit=0.1mA)
.param Phi0=2.067833848E-15
.param B0=1
.param Ic0=0.0001
.param IcRs=100u*6.859904418
.param B0Rs=IcRs/Ic0*B0
.param Rsheet=2 
.param Lsheet=1.13e-12 
.param LP=0.5p
.param IC=2.5
.param LB=2p
.param BiasCoef=0.7
.param B1=2.5
.param B2=1.67
.param B3=2.32
.param B4=2.02
.param B5=2.5
.param B6=1.69
.param B7=2.5
.param IB1=175u        
.param IB2=222u          
.param IB3=175u             
.param IB4=175u  
       
.param LB1=LB           
.param LB2=LB          
.param LB3=LB           
.param LB4=LB 
             
.param L1=1.9553p               
.param L2=3.8899p         
.param L3=8.6023p      
.param L4=2.0461p       
.param L5=3.8124p     
.param L6=4.6626p       
.param L7=1.8248p 
.param LP1=LP         
.param LP3=LP          
.param LP4=LP         
.param LP5=LP          
.param LP7=LP  
        
.param RB1=B0Rs/B1       
.param RB2=B0Rs/B2       
.param RB3=B0Rs/B3          
.param RB4=B0Rs/B4         
.param RB5=B0Rs/B5         
.param RB6=B0Rs/B6          
.param RB7=B0Rs/B7
.param LRB1=(RB1/Rsheet)*Lsheet+LP
.param LRB2=(RB2/Rsheet)*Lsheet
.param LRB3=(RB3/Rsheet)*Lsheet+LP
.param LRB4=(RB4/Rsheet)*Lsheet+LP
.param LRB5=(RB5/Rsheet)*Lsheet+LP
.param LRB6=(RB6/Rsheet)*Lsheet
.param LRB7=(RB7/Rsheet)*Lsheet+LP
B1 1 2 jjmit  area=B1 
B2 4 5 jjmit  area=B2 
B3 5 6 jjmit  area=B3 
B4 8 9 jjmit  area=B4 
B5 10 11 jjmit  area=B5 
B6 13 8 jjmit  area=B6 
B7 14 15 jjmit  area=B7 
IB1 0 3 pwl(0 0 5p IB1)
IB2 0 7 pwl(0 0 5p IB2)
IB3 0 12 pwl(0 0 5p IB3)
IB4 0 16 pwl(0 0 5p IB4)
LB1 3 1 LB1 
LB2 7 5 LB2 
LB3 12 10 LB3 
LB4 16 14 LB4 
L1 a 1 1.948E-012 
L2 1 4 3.879E-012 
L3 5 8 8.641E-012 
L4 clk 10 2.035E-012 
L5 10 13 3.799E-012 
L6 8 14 4.675E-012 
L7 14 q 1.809E-012 
LP1 2 0 3.511E-013 
LP3 6 0 3.717E-013 
LP4 9 0 4.668E-013 
LP5 11 0 4.339E-013 
LP7 15 0 4.147E-013 
RB1 1 101 RB1  
LRB1 101 0 LRB1 
RB2 4 104 RB2  
LRB2 104 5 LRB2 
RB3 5 105 RB3  
LRB3 105 0 LRB3 
RB4 8 108 RB4  
LRB4 108 0 LRB4 
RB5 10 110 RB5  
LRB5 110 0 LRB5 
RB6 13 113 RB6  
LRB6 113 8 LRB6 
RB7 14 114 RB7  
LRB7 114 0 LRB7 
.ends
* === SOURCE DEFINITION ===
.SUBCKT SOURCECELL  a q
.model jjmit jj(rtype=1, vg=2.8mv, cap=0.07pf, r0=160, rn=16, icrit=0.1ma)
.param phi0=2.067833848e-15
.param b0=1
.param ic0=0.0001
.param icrs=100u*6.859904418
.param b0rs=icrs/ic0*b0
.param rsheet=2
.param lsheet=1.13e-12
.param lp=0.5p
.param ic=2.5
.param lb=2p
.param biascoef=0.7
.param b1=2.25
.param b2=2.25
.param b3=ic
.param ib1=275u
.param ib2=b3*ic0*biascoef
.param lb1=lb
.param lb2=lb
.param l1=1p
.param l2=3.9p
.param l3=0.6p
.param l4=1.1p
.param l5=4.5p
.param l6=phi0/(4*ic*ic0)
.param lp2=lp
.param lp3=lp
.param rb1=b0rs/b1
.param rb2=b0rs/b2
.param rb3=b0rs/b3
.param lrb1=(rb1/rsheet)*lsheet
.param lrb2=(rb2/rsheet)*lsheet+lp
.param lrb3=(rb3/rsheet)*lsheet+lp
b1 2 3 jjmit  area=b1
b2 5 6 jjmit  area=b2
b3 7 8 jjmit  area=b3
ib1 0 4 pwl(0 0 5p ib1)
ib2 0 9 pwl(0 0 5p ib2)
lb1 4 3 2.825e-012
lb2 9 7 2.942e-012
l1 a 1 1.672e-012
l2 1 0 3.901e-012
l3 1 2 5.953e-013
l4 3 5 1.1e-012
l5 5 7 4.542e-012
l6 7 q 2.012e-012
lp2 6 0 3.924e-013
lp3 8 0 3.841e-013
rb1 2 102 rb1
lrb1 102 3 lrb1
rb2 5 105 rb2
lrb2 105 0 lrb2
rb3 7 107 rb3
lrb3 107 0 lrb3
.ENDS SOURCECELL
* === INPUT LOAD DEFINITION ===
.SUBCKT LOADINCELL  a q
.model jjmit jj(rtype=1, vg=2.8mv, cap=0.07pf, r0=160, rn=16, icrit=0.1ma)
.param phi0=2.067833848e-15
.param b0=1
.param ic0=0.0001
.param icrs=100u*6.859904418
.param b0rs=icrs/ic0*b0
.param rsheet=2
.param lsheet=1.13e-12
.param lp=0.5p
.param ic=2.5
.param lb=2p
.param biascoef=0.7
.param b1=ic
.param b2=ic
.param ib1=(b1+b2)*ic0*biascoef
.param lb1=lb
.param l1=phi0/(4*b1*ic0)
.param l2=phi0/(4*b1*ic0)
.param l3=phi0/(4*b2*ic0)
.param l4=phi0/(4*b2*ic0)
.param lp1=lp
.param lp2=lp
.param rb1=b0rs/b1
.param rb2=b0rs/b2
.param lrb1=(rb1/rsheet)*lsheet+lp
.param lrb2=(rb2/rsheet)*lsheet+lp
b1 1 2 jjmit  area=b1
b2 5 6 jjmit  area=b2
ib1 0 4 pwl(0 0 5p ib1)
lb1 4 3 2.336e-012
l1 a 1 2.07e-012
l2 1 3 2.088e-012
l3 3 5 2.082e-012
l4 5 q 2.072e-012
lp1 2 0 3.137e-013
lp2 6 0 3.123e-013
rb1 1 101 rb1
lrb1 101 0 lrb1
rb2 5 105 rb2
lrb2 105 0 lrb2
.ENDS LOADINCELL
* === OUTPUT LOAD DEFINITION ===
.SUBCKT LOADOUTCELL  a q
.model jjmit jj(rtype=1, vg=2.8mv, cap=0.07pf, r0=160, rn=16, icrit=0.1ma)
.param phi0=2.067833848e-15
.param b0=1
.param ic0=0.0001
.param icrs=100u*6.859904418
.param b0rs=icrs/ic0*b0
.param rsheet=2
.param lsheet=1.13e-12
.param lp=0.5p
.param ic=2.5
.param lb=2p
.param biascoef=0.7
.param b1=ic
.param b2=ic
.param ib1=(b1+b2)*ic0*biascoef
.param lb1=lb
.param l1=phi0/(4*b1*ic0)
.param l2=phi0/(4*b1*ic0)
.param l3=phi0/(4*b2*ic0)
.param l4=phi0/(4*b2*ic0)
.param lp1=lp
.param lp2=lp
.param rb1=b0rs/b1
.param rb2=b0rs/b2
.param lrb1=(rb1/rsheet)*lsheet+lp
.param lrb2=(rb2/rsheet)*lsheet+lp
b1 1 2 jjmit  area=b1
b2 5 6 jjmit  area=b2
ib1 0 4 pwl(0 0 5p ib1)
lb1 4 3 2.336e-012
l1 a 1 2.07e-012
l2 1 3 2.088e-012
l3 3 5 2.082e-012
l4 5 q 2.072e-012
lp1 2 0 3.137e-013
lp2 6 0 3.123e-013
rb1 1 101 rb1
lrb1 101 0 lrb1
rb2 5 105 rb2
lrb2 105 0 lrb2
.ENDS LOADOUTCELL
* === SINK DEFINITION ===
.SUBCKT SINKCELL  1
r1 1 0 2
.ENDS SINKCELL
* ===== MAIN =====
I_a 0 1 pwl(0 0 150p 0 153p 600u 156p 0 250p 0 253p 600u 256p 0 280p 0 283p 600u 286p 0 540p 0 543p 600u 546p 0 600p 0 603p 600u 606p 0 640p 0 643p 600u 646p 0 780p 0 783p 600u 786p 0)
XSOURCEINa SOURCECELL 1 2
XLOADINa LOADINCELL 2 3
I_clk 0 4 pulse(0 600u 20p 2p 2p 1p 100p)
XSOURCEINclk SOURCECELL 4 5
XLOADINclk LOADINCELL 5 6
XLOADOUTq LOADOUTCELL 7 8
XSINKOUTq SINKCELL 8
XDUT thmitll_dff 3 6 7
.tran 0.025p 1000p 0
.print i(L1.XDUT) p(B1.XDUT) i(L5.XDUT) p(B5.XDUT) p(B7.XDUT) p(B1.XLOADOUTq)
.end

Layout

Layout

Simulation

No runs yet. Click "Run simulation" to start.
Criteria: data_input_activity_present: pass | clock_activity_present: pass | latched_output_activity_present: pass | latched_state_tracks_output_count: pass | output_follows_latched_state_with_delay: pass | output_does_not_exceed_data_activity: pass | output_does_not_exceed_clock_activity: pass
Artifacts: output.csv stdout.txt stderr.txt report.md